The present invention relates to a nonvolatile, integrated-circuit memory array such as an electrically erasable and programmable read-only-memory (EEPROM) array. In particular, this invention relates to a circuit and method for flash-erasing EEPROMs, the method resulting a fighter distribution of positive erased threshold voltages.
EEPROMs using hot-carrier-injection programming, as opposed to Fowler-Nordheim tunneling programming, are described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM," S. Mukherjee et al., IEDM 1985 (p. 616-619) and in (b) "A 90 ns 100K Erase/Program Cycle Megabit Flash Memory,." V. Kynett et al., ISSCC 1989 (p. 140-141). The topic of reference (a) is also discussed in U.S. Pat. No. 4,698,787.
Using prior-art Fowler-Nordheim tunnel erasing methods for non-split-gate memory-cell arrays, a positive voltage is applied to the source of each cell, the control gates of the cells are grounded and the drains of the cells are allowed to float. In practice, the term "float" means a high-impedance connection to one or more voltages. A high-impedance connections may be, for example, a field-effect transistor biased in a non-conducting state.
One of the problems arising in flash EEPROMs is over-erasure of cells. An over-erased cell has a positive charge, causing the channel under the floating gate to be conductive. That over-erased conductive cell short circuits other cells in its column of parallel-connected cells. One method to compensate for over-erasure is to form the flash EEPROMs with split gates. Another method is to program all of the EEPROM cells, then apply light erasing pulses in steps, checking after each step to see whether or not all of the cells are erased. Other methods include applying alternating programming and erasing steps as described, for example, in U.S. Pat. No. 5,132,935 issued Jul. 21, 1992, and in U.S. Pat. No. 5,122,985 issued Aug. 16, 1992 and the references therein. Both patents relate to compaction, or narrowing, of the threshold voltage distributions of flash-erased cells and both patents are assigned to Texas Instruments Incorporated.
Another problem associated with prior-art flash EEPROMs has been a wide distribution of threshold voltages after a flash erase operation. One of the major challenges in current single-transistor cell flash EEPROMs is to maintain a tight threshold voltage distribution after electrical erase. One solution to the problem requires an erase algorithm that scans the voltage threshold of every cell of the device prior to terminating the erase operation. Other solutions to the problem include process and/or circuit-design improvements to narrow or "compact" the voltage threshold distribution after erase.
Patent application Ser. No. 085,427 filed Jun. 30, 1993, also assigned to Texas Instruments Incorporated, describes a flash-programming method for compacting a wide voltage threshold distribution by allowing a current path between source and drain, and with the additional requirement that the junction at lower bias should have a positive voltage (greater than about +1V with respect to the substrate). The flash-programming step narrows the distribution of threshold voltages to a range of positive values after a previously performed flash erase procedure.
Other methods have been proposed to compact the distribution of threshold voltages. One of those methods uses wordline stress to cause Fowler-Nordheim injection of electrons into the floating gate during a flash-programming step. Another flash-programming method relies on hot-electron injection into the gate and is described in "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", Yamada, et al., IEDM 1991 (p. 11.4.1-11.1.4).